1. Field of the Invention
This invention relates to semiconductor memories and more particularly to EEPROM cells and the method of manufacture thereof.
2. Description of Related Art
Referring to FIG. 1, a fragmentary sectional view of a prior art EEPROM cell 10 is shown. Cell 10 includes a P- substrate 12 with two spaced apart regions 29 and 29' in the upper surface of substrate 12. The substrate 12 and N+ regions 29 and 29' are covered for the most part with a thin film gate oxide (silicon dioxide) layer 14. Within the gate oxide layer 14 is formed a tunnel oxide window 15 through thin film gate oxide layer 14. The tunnel oxide window 15 is located above the N+ region 29' on the right of device 10. The window 15 is only partially filled with a (silicon dioxide) thin film tunnel oxide layer 23 substantially thinner than the gate oxide layer 14. A polysilicon 1 floating gate 24 is formed above and in direct contact with the gate oxide layer 14 completely covering tunnel oxide window 15 and extending over thin tunnel oxide layer 23. Above the floating gate 24 is a thin ONO three layer dielectric thin film 25. Above the ONO 25 is formed a blanket polysilicon 2 control gate (word line) layer 26. The control gate (word line) layer 26 also overlies (traversing) the floating gate 26, as well.
The problem with the device of FIG. 1 is a relatively large tunnel oxide area 23 within tunnel oxide window 15. The minimum tunnel oxide area in such a conventional cell is limited by optical resolution of the photolithographic process employed in manufacture. A smaller tunnel oxide area is needed to provide an improved coupling ratio for the cell with higher reliability and higher yield.
U.S. Pat. No. 5,273,923 of Chang et al for "Process for Fabricating an EEPROM Cell Having a Tunnel Opening which Overlaps Field Isolation Regions" shows a process for forming a tunnel opening in an EEPROM overlapping the field oxide region employing a patch region to reduce floating gate-to-substrate capacitance to produce a higher capacitance coupling ratio to improve device performance. At Col. 6, lines 14-24 it is stated "the tunnel area . . . is defined by the overlap of tunnel opening 28 and active area 12, the minimum tunnel area will be determined by the smallest dimension of the tunnel opening and the smallest dimension of the active region. . . . Accordingly tunnel area adjustments are made by modifying the dimensions of either the tunnel opening, the active region, or both." A semiconductor substrate having an active region is bounded by a field isolation region, the active region having a tunnel implant region formed therein and having an overlying gate dielectric layer. Resist material is deposited on the substrate. The resist material is then patterned to form a tunnel opening which exposes a portion of the field isolation region and the gate dielectric overlying a portion of the active region. The active region is then doped within the tunnel opening to form a patch region. Portions of the field isolation region and the gate dielectric region exposed by the tunnel opening are then etched such that the active region of the semiconductor substrate within the tunnel opening is exposed. Then a tunnel dielectric is formed on the exposed portions of the active region. Next, an electrode is formed overlying the tunnel dielectric. Alternatively, as stated at Col. 7, line 29 and following, rather than forming a patch implant, the implant step used to form the tunnel implant can be adjusted to provide sufficient out-diffusion of the tunnel implant region. Since the tunnel area is defined by the overlap of the tunnel opening and the active area, it is still determined by the photolithography alignment (overlap) of these two layers, which photolithography alignment is a problem.
U.S. Pat. No. 5,267,195 of Kodama for "Semiconductor Non-volatile Memory Device" shows a process for forming a tunnel opening in a FLOTOX structure wherein it is under the floating gate extension.